Fujitsu MB8264-20
MB8264 is a fully decoded, dynamic NMOS random access memory organized as 65536 one-bit words. The design Is optimized for high-speed, high performance applications such as mainframe memory, buffer memory, peripheral storage and environments where low power dissipation and compact layout are required. The MB8264 is fabricated using silicon-gate NMOS and Fujitsu's advanced Double-Layer Polysilicon process.| Part No. | MB8264-20 |
|---|---|
| Datasheet | MB8264-20 Download |
| Manufacturer |  Fujitsu |
| Description | NMOS Dynamic Random Access Memory |
| Buy | Stock & Price |
DESCRIPTION
The Fujitsu Multiplexed row and column address inputs permit the MB8264 to be housed In a standard 16-pln DIP. Pln-outs conform to the JEDEC approved pin out. This process, coupled with single-transistor memory storage cells, permits maximum circuit density and minimal chip size. Dynamic Circuitry Is employed in the design, including the sense amplifiers. Clock timing requirements are noncritical, and power supply tolerance is :!: 10%. All inputs/outputs are TTL compatible.FEATURES
.65,536 x 1 RAM,16-pln package● Sillcon-gate, Double Poly NMOS, single transistor cell
● Row access time: 150ns Max (MB8264-15) 200ns Max (MB8264-20)
● Cycle time: 270ns Min (MB8264-15) 330ns Min (MB8264-20)
● Low power: 22 mW Max Standby 275 mW Max Active (MB8264-15) 248 mW Max Active (MB8264-20)
● :!:10% tolerance on +5V Supply
● On-chlp substrate bias generator
● All Inputs TTL compatible, low capacitive load
● Three-state TTL compatible output
● "Gated" CAS .128 refresh cycles
● Common 110...
