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MB8264-20 - NMOS Dynamic Random Access Memory

This page provides the datasheet information for the MB8264-20, a member of the MB8264-15 NMOS Dynamic Random Access Memory family.

Datasheet Summary

Description

The Fujitsu MB8264 is a fully decoded, dynamic NMOS random access memory organized as 65536 one-bit words.

Features

  • .65,536 x 1 RAM,16-pln package.
  • Sillcon-gate, Double Poly NMOS, single transistor cell.
  • Row access time: 150ns Max (MB8264-15) 200ns Max (MB8264-20).
  • Cycle time: 270ns Min (MB8264-15) 330ns Min (MB8264-20).
  • Low power: 22 mW Max Standby 275 mW Max Active (MB8264-15) 248 mW Max Active (MB8264-20).
  • :!:10% tolerance on +5V Supply.
  • On-chlp substrate bias generator.
  • All Inputs TTL compatible, low capacitive load.
  • Three-state TTL.

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Datasheet preview – MB8264-20

Datasheet Details

Part number MB8264-20
Manufacturer Fujitsu
File Size 198.20 KB
Description NMOS Dynamic Random Access Memory
Datasheet download datasheet MB8264-20 Datasheet
Additional preview pages of the MB8264-20 datasheet.

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Full PDF Text Transcription

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FUJITSU MICROELECTRONICS NMOS 65,536·BIT DYNAMIC RANDOM ACCESS MEMORY DESCRIPTION The Fujitsu MB8264 is a fully decoded, dynamic NMOS random access memory organized as 65536 one-bit words. The design Is optimized for high-speed, high performance applications such as mainframe memory, buffer memory, peripheral storage and environments where low power dissipation and compact layout are required. Multiplexed row and column address inputs permit the MB8264 to be housed In a standard 16-pln DIP. Pln-outs conform to the JEDEC approved pin out. The MB8264 is fabricated using silicon-gate NMOS and Fujitsu's advanced Double-Layer Polysilicon process. This process, coupled with single-transistor memory storage cells, permits maximum circuit density and minimal chip size.
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