MBL80186-6 Datasheet | Fujitsu Semiconductor Limited

Feature Set: Enhanced MBl 8086-2 CPU Clock Generator 2 Independent, High-Speed DMA Channels Programmable Interrupt Controller 3 Programmable 16-bit Timers Programmable Memory and Peripheral Chip-Select logic Programmable Wait State Generator local Bus Controller - Available in 8MHz (MBl80186) and cost effective 6MHz (MBl 80186-6) versions. - High-performance Processor 2 Times the Performance of the Standard MBl8086 4 MByte/Sec Bus Bandwidth Interface - Direct Addressing Capability to 1. MByte of Memory - pletely Object Code patible with All Exist- ing MBl 8086, 88 Software - 10 New Instruction Types - High Performance Numerical Coprocessing Capability Through Intel 8087 Interface - Two Package Options: 68-Pad Ceramic l CC (Suffix -CV) (JEDEC Type A) 68-Pin Ceramic PGA (Suffix -CR) CLKOUT Fig. 1 - BLOCK DIAGRAM INT3/INTAl INT2/1NTAO CLOCK GENERATOR r EXECU--;:-I~N-U;I~ 16-81T PROGRAMMABLE INTERRUPT CONTROLLER MAX COUNT REGISTER B MAX COUNT REGISTER A CONTROL REGISTERS ,-------l-IDAQO DROl SRDY AROY TEST HOLD HLDA RESET CHIP-SELECT UNIT 20- 81T SOURCE POINTERS 20-81T DESTINATION POINTERS 16-81T TAft.NSF ER COUNT CONTROL REGISTERS Portions reprinted by permission of Intel Corporation ©Intel Corporation, 1983 ©FUJITSU LIMITED, 1986 MCSO-3 1-90...