MBL80188 Datasheet | Fujitsu Semiconductor Limited

Feature Set: Enhanced MBl 8088-2 CPU Clock Generator 2 Independent. High- Speed DMA Channels Programmable Interrupt Controller 3 Programmable 16- bit Timers Programmable Memory and Peripheral Chip-Select logic Programmable Wait State Generator local Bus Controller - 8- Bit Data Bus Interface: 16- bit internal architecture - Available in 8 MHz (MBl 80188) and cost effective 6 MHz (MBl 80188- 6) versions. - High-performance 8 MHz Processor 2 Times the Performance of the Standard MBl8088 2 MByte/Sec Bus Bandwidth Interface - Direct Addressing Capability to 1 MByte of Memory - pletely Object Code patible with All Exist- ing MBl 8086.88 Software - 10 New Instruction Types - High Performance Numerical Coprocessing Capability Through Intel 8087 Interface - Two Package Options: 68-Pad Ceramic l CC (Suffix - CV) (JEDEC Type A) 68- Pin Ceramic PGA (Suffix o CR) Fig. 1 - BLOCK DIAGRAM CLKOUT Vee GND INTlfl NTAl Portions Reprinted by permission of Intel Corporation © Intel Corporation, 1982 © FUJITSU Ll MITED,1986 MCSO-3 1- 172 DRCO ORal 20-BIT SOURCE POINTERS 20- BIT DESTINATION POINTERS l6-BIT TRANSFER COUNT CONTROL REGISTERS FUJITSU MBL 80188 MBL 80188-6 TOP VIEW Fig. 2 - PIN CONFIGURATIONS 68- PAD LCC BOTTOM VIEW PCS6/A2 PCS5/A1 PCS4 PCS3 PCS2 PCS1 Vss PCSO RES TMR OUT 1 TMR OUTO TOP VIEW 68- PIN...