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GS8161E36DD - 18Mb SyncBurst SRAMs

Download the GS8161E36DD datasheet PDF. This datasheet also covers the GS8161E18D variant, as both devices belong to the same 18mb syncburst srams family and are provided as variant models within a single manufacturer datasheet.

General Description

Applications The GS8161E18D(GT/D)/GS8161E32D(D)/GS8161D36D(GT/D) is an 18,874,368-bit high performance synchronous SRAM with a 2-bit burst address counter.

Key Features

  • FT pin for user-configurable flow through or pipeline operation.
  • Dual Cycle Deselect (DCD) operation.
  • IEEE 1149.1 JTAG-compatible Boundary Scan.
  • 2.5 V or 3.3 V +10%/.
  • 10% core power supply.
  • 2.5 V or 3.3 V I/O supply.
  • LBO pin for Linear or Interleaved Burst mode.
  • Internal input resistors on mode pins allow floating mode pins.
  • Default to Interleaved Pipeline mode.
  • Byte Write (BW) and/or Global Write (GW) opera.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (GS8161E18D-GSITechnology.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number GS8161E36DD
Manufacturer GSI Technology
File Size 1.19 MB
Description 18Mb SyncBurst SRAMs
Datasheet download datasheet GS8161E36DD Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
GS8161E18D(GT/D)/GS8161E32D(D)/GS8161E36D(GT/D) 100-Pin TQFP & 165-Bump BGA Commercial Temp Industrial Temp 1M x 18, 512K x 32, 512K x 36 18Mb SyncBurst SRAMs 400 MHz–150 MHz 2.5 V or 3.3 V VDD 2.5 V or 3.3 V I/O Features • FT pin for user-configurable flow through or pipeline operation • Dual Cycle Deselect (DCD) operation • IEEE 1149.1 JTAG-compatible Boundary Scan • 2.5 V or 3.3 V +10%/–10% core power supply • 2.5 V or 3.