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GS8170DD18C-300 - SigmaRAM SRAM

This page provides the datasheet information for the GS8170DD18C-300, a member of the GS8170DD18C SigmaRAM SRAM family.

Description

Because SigmaRAMs are synchronous devices, address and read/write control inputs are captured on the rising edge of the input clock.

Write cycles are internally self-timed and initiated by the rising edge of the clock input.

Features

  • Double Data Rate Read and Write mode.
  • JEDEC-standard SigmaRAM™ pinout and package.
  • 1.8 V +150/.
  • 100 mV core power supply.
  • 1.5 V or 1.8 V I/O supply.
  • Pipelined read operation.
  • Fully coherent read and write pipelines.
  • Echo Clock outputs track data output drivers.
  • ZQ mode pin for user-selectable output drive strength.
  • 2 user-programmable chip enable inputs for easy depth expansion.
  • IEEE 1149.1 JTAG-com.

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Datasheet preview – GS8170DD18C-300

Datasheet Details

Part number GS8170DD18C-300
Manufacturer GSI Technology
File Size 889.66 KB
Description SigmaRAM SRAM
Datasheet download datasheet GS8170DD18C-300 Datasheet
Additional preview pages of the GS8170DD18C-300 datasheet.

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Full PDF Text Transcription

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Preliminary GS8170DD18/36C-333/300/250 209-Bump BGA Commercial Temp Industrial Temp 18Mb Σ1x2Lp Double Data Rate SigmaRAM™ SRAM 250 MHz–333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Double Data Rate Read and Write mode • JEDEC-standard SigmaRAM™ pinout and package • 1.8 V +150/–100 mV core power supply • 1.5 V or 1.8 V I/O supply • Pipelined read operation • Fully coherent read and write pipelines • Echo Clock outputs track data output drivers • ZQ mode pin for user-selectable output drive strength • 2 user-programmable chip enable inputs for easy depth expansion • IEEE 1149.1 JTAG-compatible Boundary Scan • 209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package • Pin-compatible with future 36Mb, 72Mb, and 144Mb devices - 333 3.0 ns 1.
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