Datasheet4U Logo Datasheet4U.com

GS8170DD36C - Double Data Rate SigmaRAM

Description

Because SigmaRAMs are synchronous devices, address data inputs and read/write control inputs are captured on the rising edge of the input clock.

Write cycles are internally self-timed and initiated by the rising edge of the clock input.

Features

  • Double Data Rate Read and Write mode.
  • Late Write; Pipelined read operation.
  • JEDEC-standard SigmaRAM™ pinout and package.
  • 1.8 V +150/.
  • 100 mV core power supply.
  • 1.8 V CMOS Interface.
  • ZQ controlled user-selectable output drive strength.
  • Dual Cycle Deselect.
  • Burst Read and Write option.
  • Fully coherent read and write pipelines.
  • Echo Clock outputs track data output drivers.
  • 2 user-programmable c.

📥 Download Datasheet

Datasheet preview – GS8170DD36C

Datasheet Details

Part number GS8170DD36C
Manufacturer GSI Technology
File Size 809.15 KB
Description Double Data Rate SigmaRAM
Datasheet download datasheet GS8170DD36C Datasheet
Additional preview pages of the GS8170DD36C datasheet.

📁 Similar Datasheet

  • GS810C - Microprocessor Reset Monitors (Vishay Siliconix)
  • GS816118 - (GS816118 - GS816136) Sync Burst SRAMs (GSI)
  • GS816118B - (GS816118B - GS816136B) Sync Burst SRAMs (GSI)
  • GS816132 - (GS816118 - GS816136) Sync Burst SRAMs (GSI)
  • GS816132B - (GS816118B - GS816136B) Sync Burst SRAMs (GSI)
  • GS816136 - (GS816118 - GS816136) Sync Burst SRAMs (GSI)
  • GS816136B - (GS816118B - GS816136B) Sync Burst SRAMs (GSI)
  • GS8161E18 - (GS8161E18 - GS8161E36) Sync Burst SRAMs (GSI)
  • GS8161E32 - (GS8161E18 - GS8161E36) Sync Burst SRAMs (GSI)
  • GS8161E36 - (GS8161E18 - GS8161E36) Sync Burst SRAMs (GSI)
Other Datasheets by GSI Technology

Full PDF Text Transcription

Click to expand full text
GS8170DD36C-333/300/250/200 209-Bump BGA Commercial Temp Industrial Temp Features • Double Data Rate Read and Write mode • Late Write; Pipelined read operation • JEDEC-standard SigmaRAM™ pinout and package • 1.8 V +150/–100 mV core power supply • 1.8 V CMOS Interface • ZQ controlled user-selectable output drive strength • Dual Cycle Deselect • Burst Read and Write option • Fully coherent read and write pipelines • Echo Clock outputs track data output drivers • 2 user-programmable chip enable inputs • IEEE 1149.1 JTAG-compliant Serial Boundary Scan • 209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package • Pin-compatible with future 36Mb, 72Mb, and 144Mb devices 18Mb Σ1x2Lp CMOS I/O Double Data Rate SigmaRAM™ 200 MHz–333 MHz 1.8 V VDD 1.8 V I/O cueing and data transfer rates.
Published: |