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GS82583EQ18GK - 288Mb SigmaQuad-IIIe SRAM

Download the GS82583EQ18GK datasheet PDF. This datasheet also covers the GS82583EQ18GK-500 variant, as both devices belong to the same 288mb sigmaquad-iiie sram family and are provided as variant models within a single manufacturer datasheet.

Features

  • 8Mb x 36 and 16Mb x 18 organizations available.
  • 500 MHz maximum operating frequency.
  • 1.0 BT/s peak transaction rate (in billions per second).
  • 72 Gb/s peak data bandwidth (in x36 devices).
  • Separate I/O DDR Data Buses.
  • Non-multiplexed DDR Address Bus.
  • Two operations - Read and Write - per clock cycle.
  • Burst of 2 Read and Write operations.
  • 3 cycle Read Latency.
  • 1.3V nominal core voltage.
  • 1.2V, 1.3V,.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (GS82583EQ18GK-500-GSITechnology.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number GS82583EQ18GK
Manufacturer GSI Technology
File Size 296.35 KB
Description 288Mb SigmaQuad-IIIe SRAM
Datasheet download datasheet GS82583EQ18GK Datasheet

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Other Datasheets by GSI Technology

Part Number Description
GS82583EQ36GK 288Mb SigmaQuad-IIIe SRAM
GS82583ED18GK 288Mb SigmaQuad-IIIe SRAM
GS82583ED36GK 288Mb SigmaQuad-IIIe SRAM
GS82583ET18GK 288Mb SigmaDDR-IIIe SRAM
GS82583ET36GK 288Mb SigmaDDR-IIIe SRAM

Full PDF Text Transcription

Click to expand full text
GS82583EQ18/36GK-500/450/400 260-Pin BGA Commercial Temp Industrial Temp 288Mb SigmaQuad-IIIe™ Burst of 2 SRAM Up to 500 MHz 1.3V VDD 1.2V, 1.3V, or 1.5V VDDQ Features • 8Mb x 36 and 16Mb x 18 organizations available • 500 MHz maximum operating frequency • 1.0 BT/s peak transaction rate (in billions per second) • 72 Gb/s peak data bandwidth (in x36 devices) • Separate I/O DDR Data Buses • Non-multiplexed DDR Address Bus • Two operations - Read and Write - per clock cycle • Burst of 2 Read and Write operations • 3 cycle Read Latency • 1.3V nominal core voltage • 1.2V, 1.3V, or 1.5V HSTL I/O interface • Configurable ODT (on-die termination) • ZQ pin for programmable driver impedance • ZT pin for programmable ODT impedance • IEEE 1149.
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