GS82583EQ18GK Datasheet | GSI Technology

GS82583EQ18/36GK-500/450/400 260-Pin BGA mercial Temp Industrial Temp 288Mb Sigma Quad-IIIe™ Burst of 2 SRAM Up to 500 MHz 1.3V VDD 1.2V, 1.3V, or 1.5V VDDQ Features - 8Mb x 36 and 16Mb x 18 organizations available - 500 MHz maximum operating frequency - 1.0 BT/s peak transaction rate (in billions per second) - 72 Gb/s peak data bandwidth (in x36 devices) - Separate I/O DDR Data Buses - Non-multiplexed DDR Address Bus - Two operations - Read and Write - per clock cycle - Burst of 2 Read and Write operations - 3 cycle Read Latency - 1.3V nominal core voltage - 1.2V, 1.3V, or 1.5V HSTL I/O interface - Configurable ODT (on-die termination) - ZQ pin for programmable driver impedance - ZT pin for programmable ODT impedance - IEEE 1149.1 JTAG-pliant Boundary Scan - 260-pin, 14 mm x 22 mm, 1 mm ball pitch, 6/6 Ro HS- pliant BGA package Sigma Quad-IIIe™ Family Overview Sigma Quad-IIIe SRAMs are the Separate I/O half of the Sigma Quad-IIIe/Sigma DDR-IIIe family of high performance SRAMs. Although very similar to GSI's second generation of networking SRAMs (the Sigma Quad-II/Sigma DDR-II family), these third generation devices offer several new Features that help enable significantly higher performance. Clocking and Addressing Schemes The GS82583EQ18/36GK Sigma Quad-IIIe SRAMs are synchronous devices. They employ three pairs of positive and negative input clocks; one pair of master clocks, CK and CK, and two pairs of write data clocks, KD[1:0] and KD[1:0]. All six input clocks are single-ended; that is, each is received by a dedicated input buffer. CK and CK are used to latch address and control inputs, and to control all output timing. KD[1:0] and KD[1:0] are used solely to latch data inputs. Each internal read and write operation in a Sigma Quad-IIIe B2 SRAM is two times wider than the device I/O bus. An input data bus de-multiplexer is used to accumulate ining data before it is simultaneously written to the memory array. An output data multiplexer is used to...