GS82583ET18GK Datasheet | GSI Technology

GS82583ET18/36GK-675/625/550/500 260-Pin BGA mercial Temp Industrial Temp 288Mb Sigma DDR-IIIe™ Burst of 2 SRAM Up to 675 MHz 1.3V VDD 1.2V, 1.3V, or 1.5V VDDQ Features - 8Mb x 36 and 16Mb x 18 organizations available - 675 MHz maximum operating frequency - 675 MT/s peak transaction rate (in millions per second) - 48 Gb/s peak data bandwidth (in x36 devices) - mon I/O DDR Data Bus - Non-multiplexed SDR Address Bus - One operation - Read or Write - per clock cycle - Burst of 2 Read and Write operations - 3 cycle Read Latency - 1.3V nominal core voltage - 1.2V, 1.3V, or 1.5V HSTL I/O interface - Configurable ODT (on-die termination) - ZQ pin for programmable driver impedance - ZT pin for programmable ODT impedance - IEEE 1149.1 JTAG-pliant Boundary Scan - 260-pin, 14 mm x 22 mm, 1 mm ball pitch, 6/6 Ro HS- pliant BGA package Sigma DDR-IIIe™ Family Overview Sigma DDR-IIIe SRAMs are the mon I/O half of the Sigma Quad-IIIe/Sigma DDR-IIIe...