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GS82583ET36GK - 288Mb SigmaDDR-IIIe SRAM

Download the GS82583ET36GK datasheet PDF. This datasheet also covers the GS82583ET18GK variant, as both devices belong to the same 288mb sigmaddr-iiie sram family and are provided as variant models within a single manufacturer datasheet.

Features

  • 8Mb x 36 and 16Mb x 18 organizations available.
  • 675 MHz maximum operating frequency.
  • 675 MT/s peak transaction rate (in millions per second).
  • 48 Gb/s peak data bandwidth (in x36 devices).
  • Common I/O DDR Data Bus.
  • Non-multiplexed SDR Address Bus.
  • One operation - Read or Write - per clock cycle.
  • Burst of 2 Read and Write operations.
  • 3 cycle Read Latency.
  • 1.3V nominal core voltage.
  • 1.2V, 1.3V, or 1.5.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (GS82583ET18GK-GSITechnology.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number GS82583ET36GK
Manufacturer GSI Technology
File Size 321.79 KB
Description 288Mb SigmaDDR-IIIe SRAM
Datasheet download datasheet GS82583ET36GK Datasheet

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Other Datasheets by GSI Technology

Part Number Description
GS82583ET18GK 288Mb SigmaDDR-IIIe SRAM
GS82583ED18GK 288Mb SigmaQuad-IIIe SRAM
GS82583ED36GK 288Mb SigmaQuad-IIIe SRAM
GS82583EQ18GK 288Mb SigmaQuad-IIIe SRAM
GS82583EQ36GK 288Mb SigmaQuad-IIIe SRAM

Full PDF Text Transcription

Click to expand full text
GS82583ET18/36GK-675/625/550/500 260-Pin BGA Commercial Temp Industrial Temp 288Mb SigmaDDR-IIIe™ Burst of 2 SRAM Up to 675 MHz 1.3V VDD 1.2V, 1.3V, or 1.5V VDDQ Features • 8Mb x 36 and 16Mb x 18 organizations available • 675 MHz maximum operating frequency • 675 MT/s peak transaction rate (in millions per second) • 48 Gb/s peak data bandwidth (in x36 devices) • Common I/O DDR Data Bus • Non-multiplexed SDR Address Bus • One operation - Read or Write - per clock cycle • Burst of 2 Read and Write operations • 3 cycle Read Latency • 1.3V nominal core voltage • 1.2V, 1.3V, or 1.5V HSTL I/O interface • Configurable ODT (on-die termination) • ZQ pin for programmable driver impedance • ZT pin for programmable ODT impedance • IEEE 1149.
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