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GS8330DW72 - (GS8330DW36/72) 36M Double Late Write SRAM

Download the GS8330DW72 datasheet PDF. This datasheet also covers the GS8330DW36 variant, as both devices belong to the same (gs8330dw36/72) 36m double late write sram family and are provided as variant models within a single manufacturer datasheet.

General Description

Because SigmaRAMs are synchronous devices, address data inputs and read/write control inputs are captured on the rising edge of the input clock.

Write cycles are internally self-timed and initiated by the rising edge of the clock input.

Key Features

  • Double Late Write mode, Pipelined Read mode.
  • JEDEC-standard SigmaRAM™ pinout and package.
  • 1.8 V +150/.
  • 100 mV core power supply.
  • 1.8 V CMOS Interface.
  • ZQ controlled user-selectable output drive strength.
  • Dual Cycle Deselect.
  • Burst Read and Write option.
  • Fully coherent read and write pipelines.
  • Echo Clock outputs track data output drivers.
  • Byte write operation (9-bit bytes).
  • 2 user-programma.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (GS8330DW36_GSITechnology.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number GS8330DW72
Manufacturer GSI Technology
File Size 632.01 KB
Description (GS8330DW36/72) 36M Double Late Write SRAM
Datasheet download datasheet GS8330DW72 Datasheet

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Other Datasheets by GSI Technology

Part Number Description
GS8330DW36 (GS8330DW36/72) 36M Double Late Write SRAM
GS8330LW36C 36Mb 1x1Lp CMOS I/O Late Write SigmaRAM
GS832018AGT 36Mb Sync Burst SRAMs
GS832018GT 36Mb Sync Burst SRAMs
GS832018RT Rad-Tolerant SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
Preliminary GS8330DW36/72C-250/200 209-Bump BGA Commercial Temp Industrial Temp 36Mb Σ1x1Dp CMOS I/O Double Late Write SigmaRAM™ 200 MHz–250 MHz 1.8 V VDD 1.8 V I/O Features • Double Late Write mode, Pipelined Read mode • JEDEC-standard SigmaRAM™ pinout and package • 1.8 V +150/–100 mV core power supply • 1.8 V CMOS Interface • ZQ controlled user-selectable output drive strength • Dual Cycle Deselect • Burst Read and Write option • Fully coherent read and write pipelines • Echo Clock outputs track data output drivers • Byte write operation (9-bit bytes) • 2 user-programmable chip enable inputs • IEEE 1149.