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GS8330LW36C - 36Mb 1x1Lp CMOS I/O Late Write SigmaRAM

General Description

Because SigmaRAMs are synchronous devices, address data inputs and read/write control inputs are captured on the rising edge of the input clock.

Write cycles are internally self-timed and initiated by the rising edge of the clock input.

Key Features

  • Late Write mode, Pipelined Read mode.
  • JEDEC-standard SigmaRAM™ pinout and package.
  • 1.8 V +150/.
  • 100 mV core power supply.
  • 1.8 V CMOS Interface.
  • ZQ controlled user-selectable output drive strength.
  • Dual Cycle Deselect.
  • Burst Read and Write option.
  • Fully coherent read and write pipelines.
  • Echo Clock outputs track data output drivers.
  • Byte write operation (9-bit bytes).
  • 2 user-programmable chi.

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Datasheet Details

Part number GS8330LW36C
Manufacturer GSI Technology
File Size 635.05 KB
Description 36Mb 1x1Lp CMOS I/O Late Write SigmaRAM
Datasheet download datasheet GS8330LW36C Datasheet

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Full PDF Text Transcription (Reference)

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www.DataSheet4U.com Preliminary GS8330LW36/72C-250/200 209-Bump BGA Commercial Temp Industrial Temp 36Mb Σ1x1Lp CMOS I/O Late Write SigmaRAM™ 200 MHz–250 MHz 1.8 V VDD 1.8 V I/O Features • Late Write mode, Pipelined Read mode • JEDEC-standard SigmaRAM™ pinout and package • 1.8 V +150/–100 mV core power supply • 1.8 V CMOS Interface • ZQ controlled user-selectable output drive strength • Dual Cycle Deselect • Burst Read and Write option • Fully coherent read and write pipelines • Echo Clock outputs track data output drivers • Byte write operation (9-bit bytes) • 2 user-programmable chip enable inputs • IEEE 1149.