GS841Z36AT Datasheet | GSI Technology

.. GS841Z18/36AT-180/166/150/100 100-Pin TQFP mercial Temp Industrial Temp Features - 256K x 18 and 128K x 36 configurations - User-configurable Pipelined and Flow Through mode - NBT (No Bus Turn Around) functionality allows zero wait - Fully pin-patible with both pipelined and flow through Nt RAM™, No BL™ and ZBT™ SRAMs - IEEE 1149.1 JTAG-patible Boundary Scan - 3.3 V +10%/- 5% core power supply - 2.5 V or 3.3 V I/O supply - LBO pin for Linear or Interleave Burst mode - Byte write operation (9-bit Bytes) - 3 chip enable signals for easy depth expansion - Clock Control, registered, address, data, and control - ZZ Pin for automatic power-down - JEDEC-standard 100-lead TQFP package - Pb-Free 100-lead TQFP package available 4Mb Pipelined and Flow Through Synchronous NBT SRAMs 180 MHz- 100 MHz 3.3 V VDD 2.5 V and 3.3 V VDDQ Because it is a synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable (ZZ) and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates plex offchip write pulse generation required by asynchronous SRAMs and simplifies input signal timing. The GS841Z18/36AT may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, in addition to the rising-edgetriggered registers that capture input signals, the device incorporates a rising-edge-triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge-triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock. The...