Datasheet Details
| Part number | GS8161E18 |
|---|---|
| Manufacturer | GSI |
| File Size | 936.23 KB |
| Description | (GS8161E18 - GS8161E36) Sync Burst SRAMs |
| Datasheet |
 GS8161E18 Datasheet
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General Description
The GS8161E18(T/D)/GS8161E32(D)/GS8161E36(T/D) is a 18,874,368-bit high performance synchronous SRAM with a 2-bit burst address counter.
Key Features
- FT pin for user-configurable flow through or pipeline operation.
- Dual Cycle Deselect (DCD) operation.
- IEEE 1149.1 JTAG-compatible Boundary Scan.
- 2.5 V or 3.3 V +10%/.
- 10% core power supply.
- 2.5 V or 3.3 V I/O supply.
- LBO pin for Linear or Interleaved Burst mode.
- Internal input resistors on mode pins allow floating mode pins.
- Default to Interleaved Pipeline mode.
- Byte Write (BW) and/or Global Write (GW) opera.