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GS8161E32 - (GS8161E18 - GS8161E36) Sync Burst SRAMs

Download the GS8161E32 datasheet PDF. This datasheet also covers the GS8161E18 variant, as both devices belong to the same (gs8161e18 - gs8161e36) sync burst srams family and are provided as variant models within a single manufacturer datasheet.

General Description

The GS8161E18(T/D)/GS8161E32(D)/GS8161E36(T/D) is a 18,874,368-bit high performance synchronous SRAM with a 2-bit burst address counter.

Key Features

  • FT pin for user-configurable flow through or pipeline operation.
  • Dual Cycle Deselect (DCD) operation.
  • IEEE 1149.1 JTAG-compatible Boundary Scan.
  • 2.5 V or 3.3 V +10%/.
  • 10% core power supply.
  • 2.5 V or 3.3 V I/O supply.
  • LBO pin for Linear or Interleaved Burst mode.
  • Internal input resistors on mode pins allow floating mode pins.
  • Default to Interleaved Pipeline mode.
  • Byte Write (BW) and/or Global Write (GW) opera.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (GS8161E18_GSI.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number GS8161E32
Manufacturer GSI
File Size 936.23 KB
Description (GS8161E18 - GS8161E36) Sync Burst SRAMs
Datasheet download datasheet GS8161E32 Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
www.DataSheet4U.com GS8161E18(T/D)/GS816132(D)/GS816136(T/D) 100-Pin TQFP & 165-Bump BGA Commercial Temp Industrial Temp Features • FT pin for user-configurable flow through or pipeline operation • Dual Cycle Deselect (DCD) operation • IEEE 1149.1 JTAG-compatible Boundary Scan • 2.5 V or 3.3 V +10%/–10% core power supply • 2.5 V or 3.3 V I/O supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating mode pins • Default to Interleaved Pipeline mode • Byte Write (BW) and/or Global Write (GW) operation • Internal self-timed write cycle • Automatic power-down for portable applications • JEDEC-standard 100-lead TQFP and 165-bump BGA packages 1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs 250 MHz–133 MHz 2.5 V or 3.3 V VDD 2.5 V or 3.