Datasheet Details
| Part number | GS88118 |
|---|---|
| Manufacturer | GSI |
| File Size | 345.49 KB |
| Description | (GS88118 / GS88136T) Sync Burst SRAMs |
| Datasheet |
 GS88118 Datasheet
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General Description
The GS88118//36T is a 9,437,184-bit high performance synchronous SRAM with a 2-bit burst address counter.
Key Features
- FT pin for user-configurable flow through or pipelined operation.
- Single Cycle Deselect (SCD) Operation.
- IEEE 1149.1 JTAG-compatible Boundary Scan.
- On-chip write parity checking; even or odd selectable.
- 3.3 V +10%/.
- 5% core power supply.
- 2.5 V or 3.3 V I/O supply.
- LBO pin for Linear or Interleaved Burst mode.
- Internal input resistors on mode pins allow floating mode pins.
- Default to Interleaved Pipeline mode.