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HM658512A - 4 M PSRAM (512-kword x 8-bit) 2 k Refresh

General Description

The Hitachi HM658512A is a CMOS pseudo static RAM organized 512-kword × 8-bit.

It realizes higher density, higher performance and low power consumption by employing 0.8 µm Hi-CMOS process technology.

It offers low power data retention by self refresh mode.

Key Features

  • Single 5 V (±10%).
  • High speed  Access time CE access time: 70/80/100 ns (max)  Cycle time Random read/write cycle time: 115/130/160 ns (min).
  • Low power  Active: 250 mW (typ)  Standby: 200 µW (typ).
  • Directly TTL compatible All inputs and outputs.
  • Simple address configuration Non multiplexed address.
  • Refresh cycle  2048 refresh cycles: 32 ms HM658512A Series.
  • Easy refresh functions Address refresh Automatic refresh Self refresh.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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HM658512A Series 4 M PSRAM (512-kword × 8-bit) 2 k Refresh ADE-203-218C(Z) Rev. 3.0 Nov. 1997 Description The Hitachi HM658512A is a CMOS pseudo static RAM organized 512-kword × 8-bit. It realizes higher density, higher performance and low power consumption by employing 0.8 µm Hi-CMOS process technology. It offers low power data retention by self refresh mode. It also offers easy non multiplexed address interface and easy refresh functions. HM658512A is suitable for handy systems which work with battery back-up systems. The device is packaged in a small 525-mil SOP (460-mil body SOP) or a 8 × 20 mm TSOP with thickness of 1.2 mm, or a 600-mil plastic DIP. High density custom cards made of Tape Carrier Packages are also available.