SH7705
Overview
- Original Hitachi SuperH architecture
- Compatible with SH-1, SH-2 and SH-3 at object code level
- 32-bit internal data bus
- General-registers Sixteen 32-bit general registers (eight 32-bit shadow registers) Five 32-bit control registers Four 32-bit system registers
- RISC-type instruction set Instruction length: 16-bit fixed length and improved code efficiency Load/store architecture Delayed branch instructions Instruction set based on C language
- Instruction execution time: one instruction/cycle for basic instructions
- Logical address space: 4 Gbytes
- Five-stage pipeline Memory management unit (MMU)
- 4 Gbytes of address space, 256 address space identifiers (ASID: 8 bits)
- Page unit sharing
