SH7708
Overview
- Original Hitachi SuperH RISC engine architecture
- 32-bit internal data bus
- General-register machine Sixteen 32-bit general registers (eight 32-bit bank registers) Five 32-bit control registers Four 32-bit system registers
- RISC-type instruction set (upward compatibility with the SH-1 and SH-2 series) Instruction length: 16-bit fixed length for improved code efficiency Load-store architecture Delayed branch instructions C-oriented instruction set
- Instruction execution time: one instruction/cycle for basic instructions
- Logical address space: 4 Gbytes (448-Mbyte actual memory space)
- Space identifier ASID: 8 bits, 256 logical address spaces
- On-chip multiplier
- Five-stage pipeline Operating modes,
- clock pulse generator
