HD74ALVCH162836 Datasheet | Hitachi Semiconductor

Description This 20-bit universal bus driver is designed for 2.3 V to 3.6 V VCC operation. Data flow from A to Y is controlled by the output enable (O E) input. The device operates in the transparent mode when the latch enable (LE) input is low. When LE is high, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is high, the A data is stored in the latch flip flop on the low to high transition of CLK. When OE is high, the outputs are in the high impedance state. To ensure the high impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current sinking capability of the driver. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level. All outputs, which are designed to sink up to 12 m A, include 26 Ω resistors to reduce overshoot and undershoot. Features - VCC = 2.3 V to 3.6 V - Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) - Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C) - High output current ±12 m A (@VCC = 3.0 V) - Bus hold on data inputs eliminates the need for external pullup / pulldown resistors - All outputs have equivalent 26 Ω series resistors, so no external resistors are required. Function Table Inputs OE H L L L L L LE X L L H H H CLK X X X ↑ ↑ L or H A X L H L H X Z L H L H Y0 - 1 Output Y H : High level L : Low level X : Immaterial Z : High impedance ↑ : Low to high transition Note: 1. Output level before the indicated steady state input conditions were established. Pin Arrangement OE 1 Y1 2 Y2 3 GND 4 Y3 5 Y4 6 VCC 7 Y5 8 Y6 9 Y7 10 GND 11 Y8 12 Y9 13 Y10 14 Y11 15 Y12 16 Y13 17 GND 18 Y14 19 Y15 20 Y16 21 VCC 22 Y17 23 Y18 24 GND 25 Y19 26 Y20 27 NC 28 56 CLK 55 A1 54 A2 53 GND 52 A3 51 A4 50 VCC 49 A5 48 A6 47 A7 46 GND 45 A8 44 A9 43 A10 42 A11 41 A12 40 A13 39 GND 38 A14 37 A15 36 A16 35 VCC 34 A17 33 A18...