HD74HCT573 Datasheet | Hitachi Semiconductor

Description When the latch enable (LE) input is high, the Q outputs of HD74HCT563 will follow the inversion of the D inputs and the Q outputs of HD74HCT573 will follow the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enabled returns high again. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. Features - - - - - - LSTTL Output Logic Level patibility as well as CMOS Output patibility High Speed Operation: tpd (D to Q, Q) = 13 ns typ (CL = 50 p F) High Output Current: Fanout of 15 LSTTL Loads Wide Operating Voltage: VCC = 4.5 to 5.5 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Function Table Outputs Output Control L L L H Latch Enable H H L X Data H L X X HD74HCT563 L H Q0 Z HD74HCT573 H L Q0 Z HD74HCT563/HD74HCT573 Pin Arrangement HD74HCT563 Output Control 1 1D 2 2D 3 3D 4 4D 5 5D 6 6D 7 7D 8 8D 9 GND 10 OE D Q OE D Q OE D Q OE D Q OE D Q OE D Q OE D Q OE D Q 20 VCC 19 1Q 18 2Q 17 3Q 16 4Q 15 5Q 14 6Q 13 7Q 12 8Q Latch 11 Enable (Top view) HD74HCT563/HD74HCT573 Output Control 1 1D 2 2D 3 3D 4 4D 5 5D 6 6D 7 7D 8 8D 9 GND 10 OE D Q OE D Q OE D Q OE D Q OE D Q OE D Q OE D Q OE D Q 20 VCC 19 1Q 18 2Q 17 3Q 16 4Q 15 5Q 14 6Q 13 7Q 12 8Q Latch 11 Enable (Top view) HD74HCT563/HD74HCT573 Block Diagram HD74HCT563 1D 2D 3D D C Q C D C Q C D C Q C D C Q C D C Q C D C Q C D C Q C D C Q C 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 4D 5D 6D 7D 8D Enable C OC HD74HCT563/HD74HCT573 1D 2D 3D D C Q C D C Q C D C Q C D C Q C D C Q C D C Q C D C Q C D C Q C 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 4D 5D 6D 7D 8D Enable C OC Absolute Maximum Ratings Item Supply voltage range Input voltage Output voltage DC current drain per pin DC current drain per VCC, GND DC input diode current DC output diode current Power...