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HD74HCT534 - Octal D-type Flip-Flops(with inverted 3-state outputs)

General Description

These device are positive edge triggered flip-flops.

The difference between HD74HCT374 and HD74HCT534 is only that the former is a true outputs and the latter is a false outputs.

Key Features

  • LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility High Speed Operation: tpd (Clock to Q) = 15 ns typ (CL = 50 pF) High Output Current: Fanout of 15 LSTTL Loads Wide Operating Voltage: VCC = 4.5 to 5.5 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Function Table Output Control L L L H X : Z : L X Clock D H L X X HD74HCT374 Q H L No change Z HD74HCT534 Q L H No c.

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Other Datasheets by Hitachi Semiconductor (now Renesas)

Part Number Description
HD74HCT533 Octal D-type Transparent Latches(with inverted 3-state outputs)
HD74HCT540 Octal Buffers/Line Drivers (with 3-state outputs)
HD74HCT541 Octal Buffers/Line Drivers (with 3-state outputs)
HD74HCT563 Octal Transparent Latches (with 3-state outputs)
HD74HCT564 Octal D-type Flip-Flops (with 3-state outputs)

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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HD74HCT374/HD74HCT534 Octal D-type Flip-Flops (with 3-state outputs)/ Octal D-type Flip-Flops (with inverted 3-state outputs) Description These device are positive edge triggered flip-flops. The difference between HD74HCT374 and HD74HCT534 is only that the former is a true outputs and the latter is a false outputs. Data at the D inputs, meeting the setup and hold time requirements, are transferred to the Q outputs on positive going transitions of the clock (CK) input. When a high logic level is applied to the output control (OC) input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements.