HD74HCT563 Description
When the latch enable (LE) input is high, the Q outputs of HD74HCT563 will follow the inversion of the D inputs and the Q outputs of HD74HCT573 will follow the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enabled returns high again. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what...
HD74HCT563 Key Features
- LSTTL Output Logic Level patibility as well as CMOS Output patibility High Speed Operation: tpd (D to Q, Q) = 13 ns typ