HM62G36256 Datasheet | Hitachi Semiconductor

Description The HM62G36256 is a synchronous fast static RAM organized as 256-kword × 36-bit. It has realized high speed access time by employing the most advanced CMOS process and high speed circuit designing technology. It is most appropriate for the application which requires high speed, high density memory and wide bit width configuration, such as cache and buffer memory in system. It is packaged in standard 119bump BGA. Note: All power supply and ground pins must be connected for proper operation of the device. Features - - - - - - - - - - - - - Power supply: 3.3 V +10%, - 5% Clock frequency: 200 MHz to 250 MHz Internal self-timed late write Byte write control (4 byte write selects, one for each 9-bit) Optional ×18 configuration HSTL patible I/O Programmable impedance output drivers User selective input trip-point Differential, HSTL clock inputs Asynchronous G output control Asynchronous sleep mode Limited set of boundary scan JTAG IEEE 1149.1 patible Protocol: Single clock register-register mode Preliminary: The specifications of this device are subject to change without notice. Please contact your nearest Hitachi’s Sales Dept. regarding specifications. HM62G36256 Series Ordering Information Type No. HM62G36256BP-4 HM62G36256BP-5 Access time 2.1 ns 2.5 ns Cycle time 4.0 ns 5.0 ns Package 119-bump 1. 27 mm 14 mm × 22 mm BGA (BP-119A) Pin Arrangement 119-bumps BGA 1 A NC NC VDDQ SA0 SA6 SA4 SA2 VDDQ SA8 SA9 NC NC NC NC SA7 NC SA14 SA3 VDD SA5 SA1 DQc1 DQc0 VSS ZQ SS G VSS DQb0 DQb1 VSS DQb3 DQb2 VSS DQb4 VDDQ DQc2 DQc3 VSS VDDQ DQc4 VSS DQc6 DQc5 SWEc NC SWEb DQb5 DQb6 DQc7 DQc8 VSS NC VSS DQb8...