HM62V16100I Datasheet | Hitachi Semiconductor

Description The HM62V16100I Series is 16-Mbit static RAM organized 1-Mword × 16-bit. HM62V16100I Series has realized higher density, higher performance and low power consumption by employing CMOS process technology (6-transistor memory cell). It offers low power standby power dissipation; therefore, it is suitable for battery backup systems. It has the package variations of 48-bump chip size package with 0.75 mm bump pitch and 48-pin plastic TSOPI for high density surface mounting. Features - Single 3.0 V supply: 2.7 V to 3.6 V - Fast access time: 45/55 ns (max) - Power dissipation:  Active: 9 m W/MHz (typ)  Standby: 1.5 µW (typ) - pletely static memory.  No clock or timing strobe required - Equal access and cycle times - mon data input and output.  Three state output - Battery backup operation.  2 chip selection for battery backup - Temperature range: - 40 to +85°C Rev.2.00, Oct.06.2003, page 1 of 23 HM62V16100I Series Ordering Information Type No. HM62V16100LTI-4 HM62V16100LTI-4SL HM62V16100LTI-5SL HM62V16100LBPI-4 HM62V16100LBPI-4SL HM62V16100LBPI-5SL Access time 45 ns 45 ns 55 ns 45 ns 45 ns 55 ns 48-bump CSP with 0.75 mm bump pitch (TBP-48F) Package 48-pin plastic TSOPI (normal-bend type) (TFP-48DA) Rev.2.00, Oct.06.2003, page 2 of 23 HM62V16100I Series Pin Arrangement 48-pin TSOP A15 A14 A13 A12 A11 A10 A9 A8 A19 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 (Top view) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE VSS I/O15/A-1 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 VCC I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 I/O8 I/O0 CS2 NU UB LB A18 A17 A7 A6 A5 A4 A3 A2 A1 CS1 A0 Rev.2.00, Oct.06.2003, page 3 of 23 HM62V16100I Series Pin Description (TSOP) Pin name A0 to A19 A-1 to A19 I/O0 to I/O15 CS1 CS2 WE OE LB UB BYTE VCC VSS NC NU- Function Address input (word mode) Address input (byte mode) Data input/output Chip select 1 Chip select 2 Write enable Output enable Lower byte select Upper...