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H57V2562GFR Datasheet 256mb Synchronous Dram Based On 4m X 4bank X16 I/o

Manufacturer: SK Hynix

Overview: .. 256Mb Synchronous DRAM based on 4M x 4Bank x16 I/O 256M (16Mx16bit) Hynix SDRAM Memory Memory Cell Array - Organized as 4banks of 4,194,304 x 16 This document is a general.

General Description

and is subject to change without notice.

Hynix does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Key Features

  • Standard SDRAM Protocol Internal 4bank operation Power Supply Voltage : VDD = 3.3V, VDDQ = 3.3V All device pins are compatible with LVTTL interface Low Voltage interface to reduce I/O power 8,192 Refresh cycles / 64ms Programmable CAS latency of 2 or 3 Programmable Burst Length and Burst Type - 1, 2, 4, 8 or full page for Sequential Burst - 1, 2, 4 or 8 for Interleave Burst Commercial Temp : 0oC ~ 70oC Operation Package Type : 54ball, 0.8mm pitch.

More Datasheets from SK Hynix

Part Number Description
H57V2562GTR 256Mb Synchronous DRAM based on 4M x 4Bank x16 I/O
H57V2582GTR 256Mb Synchronous DRAM based on 8M x 4Bank x8 I/O
H57V2582GTR-60C 256Mb Synchronous DRAM based on 8M x 4Bank x8 I/O
H57V2582GTR-60I 256Mb Synchronous DRAM based on 8M x 4Bank x8 I/O
H57V2582GTR-60J 256Mb Synchronous DRAM based on 8M x 4Bank x8 I/O
H57V2582GTR-60L 256Mb Synchronous DRAM based on 8M x 4Bank x8 I/O
H57V2582GTR-75C 256Mb Synchronous DRAM based on 8M x 4Bank x8 I/O
H57V2582GTR-75I 256Mb Synchronous DRAM based on 8M x 4Bank x8 I/O
H57V2582GTR-75J 256Mb Synchronous DRAM based on 8M x 4Bank x8 I/O
H57V2582GTR-75L 256Mb Synchronous DRAM based on 8M x 4Bank x8 I/O

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