H5AN4G6NAFR-xxC Overview
SK hynix 4Gb DDR4 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.
H5AN4G6NAFR-xxC Key Features
- VDD=VDDQ=1.2V +/- 0.06V
- Two Termination States such as RTT_PARK and
- Fully differential clock inputs (CK, CK) operation
- Differential Data Strobe (DQS, DQS)
- Asynchronous RESET pin supported
- On chip DLL align DQ, DQS and DQS transition with CK
- ZQ calibration supported
- TDQS (Termination Data Strobe) supported (x8 only)
- DM masks write data-in at the both rising and falling edges of the data strobe
- All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock