H5ANAG4NCJR Datasheet | SK Hynix

16Gb DDR4 SDRAM 16Gb DDR4 SDRAM Lead-Free&Halogen-Free (Ro HS pliant) H5ANAG4NCJR H5ANAG8NCJR H5ANAG6NCJR - SK hynix reserves the right to change products or specifications without notice. Rev. 1.5 / Sep.2020 Revision History Revision No. 0.1 0.2 0.3 1.0 1.1 1.2 1.3 1.4 1.5 History Initial Release Modify font size and format X8 2933/3200 IDD/IPP update X8 IDD/IPP specification update X16 IDD/IPP specification update Correct t RC value x8/x16 IDD/IPP specification update x4 IDD/IPP specification update Correct IPP Specification Draft Date Apr. 2019 Aug. 2019 Oct. 2019 Dec. 2019 Dec. 2019 Mar. 2020 May. 2020 May. 2020 Sep. 2020 Remark Rev. 1.5 / Sep.2020 Description The H5ANAG4NCJR-xx C, H5ANAG8NCJR-xx C, H5ANAG6NCJR-xx C are a 16Gb CMOS Double Data Rate IV (DDR4) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. SK hynix 16Gb DDR4 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth. Device Features and Ordering Information Features - VDD=VDDQ=1.2V +/- 0.06V - Fully differential clock inputs (CK, CK) operation - Differential Data Strobe (DQS, DQS) - On chip DLL align DQ, DQS and DQS transition with CK transition - DM masks write data-in at the both rising and falling edges of the data strobe - All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock - Programmable CAS latency 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19 and 20 supported - Programmable additive latency 0, CL-1, and CL-2 supported (x4/x8 only) - Programmable CAS Write latency (CWL) = 9, 10, 11, 12, 14, 16, 18 -...