Overview: w e e Document h Title 8Gbit (1Gx8bit) S NAND Flash Memory a at Revision .D History w w
Revision No.
0.0 U 4 t . m o c Preliminary HY27UH088G(2/D)M Series 8Gbit (1Gx8bit) NAND Flash History Draft Date
May. 13. 2005 Remark
Preliminary Initial Draft. 1) Add Errata
tWH tWP 25 35 tWC 50 60 0.1 Specification Relaxed value 15 20 May. 23. 2005 1) Correct the valid Blocks Number. 0.2
Valid Blocks (max) Before After 8,196 8,192 1) Add tRSBY (Table11) - tRSBY (Dummy Busy Time for Cache Read) 0.3 - tRSBY is 5us (typ.) 2) Edit figure 18, 19 1) Add TLGA package 3) Correct Extended Read Status Register mands (Table. 19) - Figures & texts are added.
Test Conditions (ILI, ILO) VIN=VOUT=0 to 3.6V 2) Correct the test Conditions (DC Characteristics table) 0.4 VIN=VOUT=0 to Vcc (max) w
Rev 0.5 / Oct. 2005 3) Change AC Conditions table 4) Add tWW parameter ( tWW = 100ns, min) - Texts & Figures are added. - tWW is added in AC timing characteristics table. 5) Edit System Interface Using CE don’t care Figures. w w .D t a S a e h t e U 4 .c m o Preliminary Jun. 13. 2005 Preliminary Jun. 14. 2005 Preliminary Sep. 16. 2005 Preliminary 6) Correct Address Cycle Map. w w w .D at h S a t e e 4U . m o c 1 Preliminary HY27UH088G(2/D)M Series 8Gbit (1Gx8bit) NAND Flash Revision History
Revision No. History
7) Correct PKG dimension (TSOP PKG) CP Before After 0.050 0.100 -Continued- Draft Date Remark 8) Delete the 1.