HY57V121620LT Datasheet PDF (Synchronous DRAM) | Download Hynix Semiconductor HY57V121620LT

HY57V121620LT - Synchronous DRAM

This page provides the datasheet information for the HY57V121620LT, a member of the HY57V121620T Synchronous DRAM family.

Description

The HY57V121620 is a 512-Mbit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth.

HY57V121620 is organized as 4banks of 8,388,608x16.

Features

Single 3.3±0.3V power supply All device pins are compatible with LVTTL interface JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch All inputs and outputs referenced to positive edge of system clock Data mask function by UDQM, LDQM Internal four banks operation.
Auto refresh and self refresh 8192 refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4, 8 or Full page for Sequential Burst.
- 1,.

Datasheet Details

Part number	HY57V121620LT
Manufacturer	Hynix Semiconductor
File Size	186.66 KB
Description	Synchronous DRAM
Datasheet	HY57V121620LT Datasheet
Additional preview pages of the HY57V121620LT datasheet.

📁 Similar Datasheet

HY57V28420BLT - 4Banks x 8M x 4bits Synchronous DRAM (Hynix)

HY57V28420BT - 4Banks x 8M x 4bits Synchronous DRAM (Hynix)

HY57V561620BLT-H - DRAM (Pioneer)

HY57V641620FTP - Synchronous DRAM Memory 64Mbit (Hynix)

HY57V641620LTP - Synchronous DRAM Memory 64Mbit (Hynix)

HY57V641620STP - Synchronous DRAM Memory 64Mbit (Hynix)

HY5-P - Current Transducers HY 5 to 25-P (LEM)

HY50-P - Current Transducer HY 50-P (LEM)

HY5002 - 1-chip composed of high-current totem pole (HAWYANG)

HY5012A - N-Channel Enhancement Mode MOSFET (HOOYI)

Full PDF Text Transcription

Click to expand full text

www.DataSheet4U.com HY57V121620(L)T 4 Banks x 8M x 16Bit Synchronous DRAM DESCRIPTION The HY57V121620 is a 512-Mbit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V121620 is organized as 4banks of 8,388,608x16. HY57V121620 is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.

Published: Feb 22, 2007 |