HY57V161610D-I Datasheet PDF (2 Banks x 512K x 16 Bit Synchronous DRAM) | Download Hynix Semiconductor HY57V161610D-I

HY57V161610D-I - 2 Banks x 512K x 16 Bit Synchronous DRAM

Description

THE Hynix HY57V161610D is a 16,777,216-bits CMOS Synchronous DRAM, ideally suited for the Mobile applications which require low power consumption and industrial temperature range.

HY57V161610D is organized as 2banks of 524,288x16.

Features

Single 3.0V to 3.6V power supplyNote1).
Auto refresh and self refresh.
All device pins are compatible with LVTTL interface.
4096 refresh cycles / 64ms.
JEDEC standard 400mil 50pin TSOP-II with 0.8mm of pin pitch.
All inputs and outputs referenced to positive edge of system clock.
Data mask function by UDQM/LDQM.
Programmable Burst Length and Burst Type - 1, 2, 4, 8 and Full Page for Sequence Burst - 1, 2, 4 and 8 for I.

Datasheet Details

Part number	HY57V161610D-I
Manufacturer	Hynix Semiconductor
File Size	161.62 KB
Description	2 Banks x 512K x 16 Bit Synchronous DRAM
Datasheet	HY57V161610D-I Datasheet
Additional preview pages of the HY57V161610D-I datasheet.

📁 Similar Datasheet

HY57V28420BLT - 4Banks x 8M x 4bits Synchronous DRAM (Hynix)

HY57V28420BT - 4Banks x 8M x 4bits Synchronous DRAM (Hynix)

HY57V561620BLT-H - DRAM (Pioneer)

HY57V641620FTP - Synchronous DRAM Memory 64Mbit (Hynix)

HY57V641620LTP - Synchronous DRAM Memory 64Mbit (Hynix)

HY57V641620STP - Synchronous DRAM Memory 64Mbit (Hynix)

HY5-P - Current Transducers HY 5 to 25-P (LEM)

HY50-P - Current Transducer HY 50-P (LEM)

HY5002 - 1-chip composed of high-current totem pole (HAWYANG)

HY5012A - N-Channel Enhancement Mode MOSFET (HOOYI)

Full PDF Text Transcription

Click to expand full text

HY57V161610D-I 2 Banks x 512K x 16 Bit Synchronous DRAM DESCRIPTION THE Hynix HY57V161610D is a 16,777,216-bits CMOS Synchronous DRAM, ideally suited for the Mobile applications which require low power consumption and industrial temperature range. HY57V161610D is organized as 2banks of 524,288x16. HY57V161610D is offering fully synchronous operation referenced to a positive edge clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.

Published: Oct 15, 2015 |