HY57V161610D Datasheet PDF (2 Banks x 512K x 16 Bit Synchronous DRAM) | Download Hynix Semiconductor HY57V161610D

HY57V161610D - 2 Banks x 512K x 16 Bit Synchronous DRAM

Description

THE Hynix HY57V161610D is a 16,777,216-bits CMOS Synchronous DRAM, ideally suited for the Mobile applications which require low power consumption and industrial temperature range.

HY57V161610D is organized as 2banks of 524,288x16.

Features

Single 3.0V to 3.6V power supply Note1).
Auto refresh and self refresh 4096 refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4, 8 and Full Page for Sequence Burst All device pins are compatible with LVTTL interface JEDEC standard 400mil 50pin TSOP-II with 0.8mm of pin pitch.
All inputs and outputs referenced to positive edge of system clock - 1, 2, 4 and 8 for Interleave Burst.
Programmable C.

Datasheet Details

Part number	HY57V161610D
Manufacturer	Hynix Semiconductor
File Size	73.20 KB
Description	2 Banks x 512K x 16 Bit Synchronous DRAM
Datasheet	HY57V161610D Datasheet
Additional preview pages of the HY57V161610D datasheet.

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Full PDF Text Transcription

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HY57V161610D 2 B a n k s x 5 1 2 K x 1 6 B it S y n c h r o n o u s D R A M DESCRIPTION THE Hynix HY57V161610D is a 16,777,216-bits CMOS Synchronous DRAM, ideally suited for the Mobile applications which require low power consumption and industrial temperature range. HY57V161610D is organized as 2banks of 524,288x16. HY57V161610D is offering fully synchronous operation referenced to a positive edge clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.

Published: Apr 2, 2005 |