HY57V283220LT 4 Banks x 1M x 32Bit Synchronous DRAM Datasheet

HY57V283220LT Key Features

JEDEC standard 3.3V power supply All device pins are patible with LVTTL interface 86TSOP-II, 90Ball FBGA with 0.8mm of p
Internal four banks operation
Burst Read Single Write operation Programmable CAS Latency ; 2, 3 Clocks
Auto refresh and self refresh 4096 refresh cycles / 64ms Programmable Burst Length and Burst Type
1, 2, 4, 8 or full page for Sequential Burst
1, 2, 4 or 8 for Interleave Burst

Part Number	Description
HY57V283220LTP	4 Banks x 1M x 32Bit Synchronous DRAM
HY57V283220T	4 Banks x 1M x 32Bit Synchronous DRAM
HY57V283220TP	4 Banks x 1M x 32Bit Synchronous DRAM
HY57V281620A	4 Banks x 2M x 16bits Synchronous DRAM
HY57V281620ELT	Synchronous DRAM Memory