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HY57V281620ELT - Synchronous DRAM Memory

General Description

and is subject to change without notice.

Hynix does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Key Features

  • Voltage: VDD, VDDQ 3.3V supply voltage All device pins are compatible with LVTTL interface 54 Pin TSOPII (Lead or Lead Free Package) All inputs and outputs referenced to positive edge of system clock Data mask function by UDQM, LDQM.
  • Internal four banks operation.
  • Burst Read Single Write operation Programmable CAS Latency; 2, 3 Clocks.
  • Auto refresh and self refresh 4096 Refresh cycles / 64m.

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Other Datasheets by SK Hynix

Part Number Description
HY57V281620ELTP Synchronous DRAM Memory 128Mbit (8M x 16bit)
HY57V281620EST Synchronous DRAM Memory 128Mbit (8M x 16bit)
HY57V281620ET Synchronous DRAM Memory 128Mbit (8M x 16bit)
HY57V281620ETP Synchronous DRAM Memory 128Mbit (8M x 16bit)
HY57V281620A 4 Banks x 2M x 16bits Synchronous DRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O Document Title 4Bank x 2M x 16bits Synchronous DRAM Revision History Revision No. 1.0 1.1 First Version Release 1. Corrected PIN ASSIGNMENT A12 to NC History Draft Date Dec. 2004 Jan. 2005 Remark This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.1 / Jan. 2005 1 Synchronous DRAM Memory 128Mbit (8Mx16bit) HY57V281620E(L)T(P) Series DESCRIPTION The Hynix HY57V281620E(L)T(P) series is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth. HY57V281620E(L)T(P) series is organized as 4banks of 2,097,152 x 16.