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HY57V281620ELT Datasheet Synchronous Dram Memory

Manufacturer: SK Hynix

Overview: 128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O Document Title 4Bank x 2M x 16bits Synchronous DRAM Revision History Revision No. 1.0 1.1 First Version Release 1. Corrected PIN ASSIGNMENT A12 to NC History Draft Date Dec. 2004 Jan.

General Description

and is subject to change without notice.

Hynix does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Key Features

  • Voltage: VDD, VDDQ 3.3V supply voltage All device pins are compatible with LVTTL interface 54 Pin TSOPII (Lead or Lead Free Package) All inputs and outputs referenced to positive edge of system clock Data mask function by UDQM, LDQM.
  • Internal four banks operation.
  • Burst Read Single Write operation Programmable CAS Latency; 2, 3 Clocks.
  • Auto refresh and self refresh 4096 Refresh cycles / 64m.

More Datasheets from SK Hynix

Part Number Description
HY57V281620ELTP Synchronous DRAM Memory 128Mbit (8M x 16bit)
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HY57V281620ET Synchronous DRAM Memory 128Mbit (8M x 16bit)
HY57V281620ETP Synchronous DRAM Memory 128Mbit (8M x 16bit)
HY57V281620A 4 Banks x 2M x 16bits Synchronous DRAM
HY57V281620FLTP Synchronous DRAM Memory 128Mbit (8Mx16bit)
HY57V281620FSTP Synchronous DRAM Memory 128Mbit (8Mx16bit)
HY57V281620FTP Synchronous DRAM Memory 128Mbit (8Mx16bit)
HY57V281620HCT (HY57V281620HC(L/S)T) 4 Banks x 2M x 16-Bits SDRAM
HY57V281620HLT (HY57V281620HC(L/S)T) 4 Banks x 2M x 16-Bits SDRAM

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