HY57V281620A Overview
The Hynix HY57V281620A is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the Mobile applications which require low power consumption and extended temperature range . A l l i n p u t s a n d o u t p u t s a r e s y n ch r o nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth.
HY57V281620A Key Features
- Single 3.3±0.3V power supply All device pins are patible with LVTTL interface JEDEC standard 400mil 54pin TSOP-II with 0
- 1, 2, 4, 8 or Full page for Sequential Burst
- All inputs and outputs referenced to positive edge of system clock
- Data mask function by UDQM or LDQM Internal four banks operation
- 1, 2, 4 or 8 for Interleave Burst Programmable CAS Latency ; 2, 3 Clocks
- Auto refresh and self refresh 4096 refresh cycles / 64ms Programmable Burst Length and Burst Type