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HY57V281620A - 4 Banks x 2M x 16bits Synchronous DRAM

General Description

low power consumption and extended temperature range .

Key Features

  • Single 3.3±0.3V power supply All device pins are compatible with LVTTL interface JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch - 1, 2, 4, 8 or Full page for Sequential Burst.
  • All inputs and outputs referenced to positive edge of system clock.
  • Data mask function by UDQM or LDQM Internal four banks operation.
  • - 1, 2, 4 or 8 for Interleave Burst Programmable CAS Latency ; 2, 3 Clocks.
  • Auto.

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Datasheet Details

Part number HY57V281620A
Manufacturer SK Hynix
File Size 81.40 KB
Description 4 Banks x 2M x 16bits Synchronous DRAM
Datasheet download datasheet HY57V281620A Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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HY57V281620A 4 Banks x 2M x 16bits Synchronous DRAM DESCRIPTION The Hynix HY57V281620A is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the Mobile applications which require low power consumption and extended temperature range . HY57V281620A is organized as 4banks of 2,097,152x16 H Y 5 7 V 2 8 1 6 2 0 A i s o f f e r i n g f u l l y s y n c h r o n o u s o p e r a t i o n r e f e r e n c e d t o a p o s i t i v e e d g e o f t h e c l o c k . A l l i n p u t s a n d o u t p u t s a r e s y n ch r o nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.