HY57V56820BLT Datasheet PDF (4 Banks x 8M x 8Bit Synchronous DRAM) | Download Hynix Semiconductor HY57V56820BLT

HY57V56820BLT - 4 Banks x 8M x 8Bit Synchronous DRAM

This page provides the datasheet information for the HY57V56820BLT, a member of the HY57V56820BT 4 Banks x 8M x 8Bit Synchronous DRAM family.

Description

The HY57V56820B is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth.

The HY57V56820B is organized as 4banks of 8,388,608x8.

Features

Single 3.3±0.3V power supply All device pins are compatible with LVTTL interface JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch All inputs and outputs referenced to positive edge of system clock Data mask function by DQM Internal four banks operation.
Auto refresh and self refresh 8192 refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4, 8 or Full page for Sequential Burst.
- 1, 2, 4 o.

Datasheet Details

Part number	HY57V56820BLT
Manufacturer	SK Hynix
File Size	173.15 KB
Description	4 Banks x 8M x 8Bit Synchronous DRAM
Datasheet	HY57V56820BLT Datasheet
Additional preview pages of the HY57V56820BLT datasheet.

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Full PDF Text Transcription

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www.DataSheet4U.com HY57V56820B(L)T 4 Banks x 8M x 8Bit Synchronous DRAM DESCRIPTION The HY57V56820B is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. The HY57V56820B is organized as 4banks of 8,388,608x8. The HY57V56820B is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.

Published: Mar 16, 2007 |