HY57V56820CLT Overview
The HY57V56820C is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. The HY57V56820C is organized as 4banks of 8,388,608x8. The HY57V56820C is offering fully synchronous operation referenced to a positive edge of the clock.
HY57V56820CLT Key Features
- Single 3.3±0.3V power supply All device pins are patible with LVTTL interface JEDEC standard 400mil 54pin TSOP-II with 0
- Auto refresh and self refresh 8192 refresh cycles / 64ms Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst Programmable CAS Latency ; 2, 3 Clocks