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HY57V641620HG - 4 Banks x 1M x 16Bit Synchronous DRAM

General Description

and is subject to change without notice.

Hyundai Electronics does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Key Features

  • Single 3.3± 0 . 3 V power supply Note).
  • Auto refresh and self refresh 4096 refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4, 8 or Full page for Sequential Burst All device pins are compatible with LVTTL interface JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch.
  • All inputs and outputs referenced to positive edge of system clock - 1, 2, 4 or 8 for Interleave Burst.
  • Programmable.

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Datasheet Details

Part number HY57V641620HG
Manufacturer SK Hynix
File Size 86.74 KB
Description 4 Banks x 1M x 16Bit Synchronous DRAM
Datasheet download datasheet HY57V641620HG Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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HY57V641620HG 4 Banks x 1M x 16Bit Synchronous DRAM D E S C R IP T IO N The Hynix HY57V641620HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V641620HG is organized as 4banks of 1,048,576x16. HY57V641620HG is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.