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HY5DU56422DT - (HY5DU56xx22DT) 256Mb DDR SDRAM

General Description

and is subject to change without notice.

Hynix Semiconductor does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Key Features

  • ES VDD, VDDQ = 2.5V +/- 0.2V for DDR200, 266, 333 VDD, VDDQ = 2.6V +/- 0.1V for DDR400 All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation.
  • All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock Programmable CAS latency 2/2.5 (DDR200, 266, 333) and 3 (DDR400) supported Programmable burst length 2/4/8 with both sequential and interleave mode Internal four bank operat.

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Full PDF Text Transcription for HY5DU56422DT (Reference)

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www.DataSheet4U.com 256Mb DDR SDRAM 256Mb DDR SDRAM HY5DU56422D(L)T HY5DU56822D(L)T HY5DU561622D(L)T This document is a general product description and is subject to chan...

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.0 /Oct. 2004 1 www.DataSheet4U.com HY5DU56422D(L)T HY5DU56822D(L)T HY5DU561622D(L)T Revision History Revision No. History First Version ReleaseMerged HY5DU564(8,16)22D(L)T and HY5DU564(8,16)22D(L)T-D into HY5DU564(8,16)22D(L)T. Draft Date Remark 1.0 Oct. 2004 Rev. 1.0 /Oct. 2004 2 www.DataSheet4U.

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