HY5DU56422DTP
Overview
- VDD, VDDQ = 2.5V +/- 0.2V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) x16 device has two bytewide data strobes (UDQS, LDQS) per each x8 I/O Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) On chip DLL align DQ and DQS transition with CK transition DM mask write data-in at the both rising and falling edges of the data strobe * * * * * * * *
- All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock Programmable CAS latency 1.5, 2, 2.5 and 3 supported Programmable burst
