HY5DU56822BT-D43 Overview
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HY5DU56822BT-D43 Key Features
- VDD/VDDQ = 2.5 ~ 2.7V All inputs and outputs are patible with SSTL_2 interface Fully differential clock inputs (CK, /CK)
- data transaction aligned to bidirectional data strobe (DQS) x16 device has two bytewide data strobes (UDQS, LDQS) per ea
- Note : D of speed indicates DDR400