HY5DU56822CT Datasheet PDF ((HY5DU56xx22CT) 256M-P DDR SDRAM) | Download Hynix Semiconductor HY5DU56822CT

HY5DU56822CT - (HY5DU56xx22CT) 256M-P DDR SDRAM

This page provides the datasheet information for the HY5DU56822CT, a member of the HY5DU56422CT (HY5DU56xx22CT) 256M-P DDR SDRAM family.

Description

and is subject to change without notice.

Hynix semiconductor does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Features

VDD/VDDQ = 2.5 ~ 2.7V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) x16 device has two bytewide data strobes (UDQS, LDQS) per each x8 I/O Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) On chip DLL align D.

Datasheet Details

Part number	HY5DU56822CT
Manufacturer	SK Hynix
File Size	267.11 KB
Description	(HY5DU56xx22CT) 256M-P DDR SDRAM
Datasheet	HY5DU56822CT Datasheet
Additional preview pages of the HY5DU56822CT datasheet.

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Full PDF Text Transcription

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www.DataSheet4U.com HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 256M-P DDR SDRAM HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.3 / Oct. 2003 HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43 DESCRIPTION PRELIMINARY The Hynix HY5DU56422, HY5DU56822 and HY5DU561622 are a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth.

Published: Mar 21, 2007 |