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HY5DU56822E - (HY5DU56822E / HY5DU561622E) 256Mb DDR SDRAM

General Description

and is subject to change without notice.

Hynix Semiconductor does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Key Features

  • VDD, VDDQ = 2.5V +/- 0.2V for DDR200, 266, 333 VDD, VDDQ = 2.6V +0.1V / -0.2V for DDR400 All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) x16 device has two bytewide data strobes (UDQS, LDQS) per each x8 I/O Data outputs on DQS edges when read (edged DQ) Data.

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Datasheet Details

Part number HY5DU56822E
Manufacturer SK Hynix
File Size 292.14 KB
Description (HY5DU56822E / HY5DU561622E) 256Mb DDR SDRAM
Datasheet download datasheet HY5DU56822E Datasheet

Full PDF Text Transcription for HY5DU56822E (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for HY5DU56822E. For precise diagrams, and layout, please refer to the original PDF.

www.DataSheet4U.com 256Mb DDR SDRAM HY5DU56822E(L)TP HY5DU561622E(L)TP This document is a general product description and is subject to change without notice. Hynix Semic...

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oduct description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.1 /June. 2006 1 www.DataSheet4U.com HY5DU56822E(L)TP HY5DU561622E(L)TP 1 Revision History Revision No. 1.0 1.1 First release Added CL2 & CL2.5 values to the DDR400B in the AC CHARACTERISTICS History Draft Date Apr. 2006 June 2006 Remark Rev. 1.1 /June. 2006 2 www.DataSheet4U.

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