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HY5DU56822EFP - (HY5DU561622EFP / HY5DU56822EFP) 256Mb DDR SDRAM

This page provides the datasheet information for the HY5DU56822EFP, a member of the HY5DU561622EFP (HY5DU561622EFP / HY5DU56822EFP) 256Mb DDR SDRAM family.

Description

and is subject to change without notice.

Hynix Semiconductor does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Features

  • VDD, VDDQ = 2.5V ± 0.2V for DDR200, 266, 333 VDD, VDDQ = 2.6V +0.1V / -0.2V for DDR400 All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) x16 device has two bytewide data strobes (UDQS, LDQS) per each x8 I/O Data outputs on DQS edges when read (edged DQ) Data i.

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Datasheet Details

Part number HY5DU56822EFP
Manufacturer SK Hynix
File Size 275.90 KB
Description (HY5DU561622EFP / HY5DU56822EFP) 256Mb DDR SDRAM
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www.DataSheet4U.com 256Mb DDR SDRAM HY5DU56822E(L)FP HY5DU561622E(L)FP This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.1 / June 2006 1 HY5DU56822E(L)FP HY5DU561622E(L)FP 1 Revision History Revision No. 1.0 1.1 First release Added CL2 & CL2.5 values to the DDR400B in the AC CHARACTERISTICS History Draft Date Apr. 2006 June 2006 Remark Rev. 1.1 / June 2006 2 HY5DU56822E(L)FP HY5DU561622E(L)FP 1 DESCRIPTION The HY5DU56822E(L)FP, and HY5DU561622E(L)FP are a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth.
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