HY5DU56822T
description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.7/May. 02 1 m o .c U 4 t e e h S a at .D w w w
HY5DU56422(L)T HY5DU56822(L)T HY5DU561622(L)T
Revision History
1. Revision 0.4 (Nov. 01)
1) Removed ‘Preliminary’
2. Revision 0.5 (Dec. 01)
1) Separated ‘Function description
’ and ‘Timing diagram’ parts
- These are available in Web site (.hynix.) 3. Revision 0.6 (May. 02) 1) Input leakage current changed from +/-5u A to +/-2u A 4. Revision 0.7 (May. 02) 1) Added ‘t RAS Lock-out function supported’
Rev. 0.7/May. 02
HY5DU56422(L)T HY5DU56822(L)T HY5DU561622(L)T DESCRIPTION
The Hynix HY5DU56422, HY5DU56822 and HY5DU561622 are a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. The Hynix 256Mb DDR SDRAMs offer fully synchronous operations...
