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HY5RS123235BFP - 512Mbit GDDR3 SDRAM

General Description

and is subject to change without notice.

responsibility for use of circuits described.

No patent licenses are implied.

Key Features

  • 2.05V/ 1.8V power supply supports (For more detail, Please see the Table 12 on page 43).
  • Single ended READ Strobe (RDQS) per byte.
  • Single ended WRITE Strobe (WDQS) per byte.
  • Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle.
  • On Die Termination.
  • Output Driver Strength adjustment by EMRS.
  • Calibrated output driver.
  • Differential clock inputs (CK and CK#).
  • Commands entered on eac.

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HY5RS123235BFP 512Mbit (16Mx32) GDDR3 SDRAM HY5RS123235BFP This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.2 / Jul. 2007 1 HY5RS123235BFP Revision History Revision No. History Draft Date Remark 0.0 Defined target spec. Apr. 2006 Preliminary 1. Changed tDH/S from 140ps to 130ps on 1GHz 2. Changed a VID(AC) value from 0.5/VDDQ+0.5 to 0.22/ 1.0 VDDQ+0.3 (Min/Max) on page 46. 4. Changed PKG bottom mold on page 59. 5. Changed tRAS_max from 100K tCK to 70Kns on page 54. 6. Revised typo. Oct. 2006 1.1 Revised Appendix C about the boundary sacn test on page 62. Nov. 2006 1. Updated IDD6 value on page 47. 1.2 2.