HY5RS123235FP-2
description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.3 / Feb. 2006 1
HY5RS123235FP Revision History
Revision No. 0.1 0.2 History Defined target spec. Page 11) Add Cas Latency 11 Page 14) Write Latency definitions Page15) DI, WR_A, AL definitions Page47) Table18 typo corrected Page48) Table19 renewered Page50) note 46 added Page4) Ballout configurations correct Appendix C) BST function description
- Non-Consectutive Read to Write timing clarifications
- Read to Precharge timing Clarifications
- Modified the pin descriptions and added mand description for BST
- Added the LP mode feature for EMRS -Added the Lead free package part number and Package dimension page Draft Date Mar. 2004 JULY.2004 CL WL DI/WR_A/AL Speed BIN Several Parameters t RPRE A3/A8/A9/A10 Page28 page41 Page23 Page4,6,21 Page15,16 Jan.31,2005 Page3,56 Remark
0.3 0.4
Aug.2004 Sep.24,2004
No...
