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HY5S6B6D - (HY5S6B6D/L/S/F/P) 4Banks x 1M x 16-Bits SDRAM

General Description

and is subject to change without notice.

Hynix does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Key Features

  • Standard SDRAM Protocol Internal 4bank operation.
  • Power Supply Voltage : VDD = 1.8V, VDDQ = 1.8V LVCMOS compatible I/O Interface Low Voltage interface to reduce I/O power Low Power Features - PASR(Partial Array Self Refresh) - AUTO TCSR (Temperature Compensated Self Refresh) - DS (Drive Strength) - Deep Power Down Mode Programmable CAS latency of 1, 2 or 3 Package Type : 54ball, 0.8mm pitch FBGA (Lead Free, Lead) HY5S6B6D(L/S)FP : Lead Free HY5S6B6D(L/S)F : Lead.

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Datasheet Details

Part number HY5S6B6D
Manufacturer SK Hynix
File Size 386.10 KB
Description (HY5S6B6D/L/S/F/P) 4Banks x 1M x 16-Bits SDRAM
Datasheet download datasheet HY5S6B6D Datasheet

Full PDF Text Transcription for HY5S6B6D (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for HY5S6B6D. For precise diagrams, and layout, please refer to the original PDF.

Document Title 4Bank x 1M x 16bits Synchronous DRAM Revision History w w w Revision No. 0.1 0.2 0.3 Initial Draft .D at h S a t e e 4U . m o c HY5S6B6D(L/S)F(P)-xE 4Banks...

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Initial Draft .D at h S a t e e 4U . m o c HY5S6B6D(L/S)F(P)-xE 4Banks x1M x 16bits Synchronous DRAM History Draft Date Sep. 2003 Oct. 2003 Nov. 2003 July 2004 Remark Preliminary Preliminary Append Super-Low Power Group to the Data-sheet Changed DC Characteristics Changed Package Information w w w .D t a S a e h t e U 4 .c m o This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 0.3 / July 2004 1 w w w .D at h S a t e e 4U .

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