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HY62UF16806A - 512Kx16bit full CMOS SRAM

General Description

and is subject to change without notice.

Hynix Semiconductor Inc does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Key Features

  • Fully static operation and Tri-state output.
  • TTL compatible inputs and outputs.
  • Battery backup(LL/SL-part) - 1.2V(min) data retention.
  • Standard pin configuration - 48-uBGA Operation Current/Icc(mA) 4 4 Standby Current(uA) LL SL 25 8 25 8 Temperature (°C) 0~70 -40~85 PIN.

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Full PDF Text Transcription for HY62UF16806A (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for HY62UF16806A. For precise diagrams, and layout, please refer to the original PDF.

www.DataSheet4U.com HY62UF16806A Series 512Kx16bit full CMOS SRAM Document Title 512K x16 bit 3.0V Super Low Power Full CMOS slow SRAM Revision History Revision No 00 01 ...

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uper Low Power Full CMOS slow SRAM Revision History Revision No 00 01 History Initial Draft Change Logo - Hyundai à Hynix Change DC Parameter - Isb1(LL) : 40uA à - Isb1(Typ) : 8uA à - Icc : 5mA à - Icc1(1us) : 8mA à - Icc1(Min) : 50mA à Change Data Retention - IccDR(LL) : 25uA à Change AC Parameter - tOE : 35ns à : 40ns à - tCW : 50ns à - tAW : 50ns à - tBW : 50ns à - tWP : 45ns à - tCHZ : 30ns à - tOHZ : 30ns à - tBHZ : 30ns à 25uA 1uA 4mA 4mA 40mA 15uA 25ns@55ns 35ns@70ns 45ns@55ns 45ns@55ns 45ns@55ns 45ns@55ns 20ns@55ns , 30ns à 25ns@70ns 20ns@55ns , 30ns à 25ns@70ns 20ns@55ns , 30ns à 25ns@70ns Mar.15.2002 Draft Date F