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HY64LD16162M - 1M x 16 bit Low Low Power 1T/1C Pseudo SRAM

General Description

- Power Up & Deep Power Down Exit Sequence Mar.

11.

‘ 02 Final Feb.

Key Features

  • CMOS Process Technology.
  • 1M x 16 bit Organization.
  • TTL compatible and Tri-state outputs.
  • Deep Power Down : Memory cell data hold invalid.
  • Standard pin configuration : 48-FBGA.
  • Data mask function by /LB, /UB.

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Datasheet Details

Part number HY64LD16162M
Manufacturer SK Hynix
File Size 282.86 KB
Description 1M x 16 bit Low Low Power 1T/1C Pseudo SRAM
Datasheet download datasheet HY64LD16162M Datasheet

Full PDF Text Transcription for HY64LD16162M (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for HY64LD16162M. For precise diagrams, and layout, please refer to the original PDF.

www.DataSheet4U.com HY64LD16162M Series Document Title 1M x 16 bit Low Low Power 1T/1C Pseudo SRAM Revision history Revision No. History 1.0 1.1 Initial Revised - Change ...

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evision history Revision No. History 1.0 1.1 Initial Revised - Change Pin Connection - Improve tOE from 45ns to 30ns - Correct State Diagram 1.2 Revised - Correct Package Dimension - Change Absolute Maximum Ratings 1.3 Revised - DC Electrical Characteristics ( IDPD,ICC1) - State Diagram - Power Up Sequence - Deep Power Down Sequence - Read/Write Cycle Note 1.4 1.5 Revised - DC Electrical Characteristics ( ICC1: 3mA - > 5mA) Revised - Improve Standby Current ISB1 from 100uA to 80uA - Power Up Sequence 1.

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