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ICS558-01 - PECL/CMOS TO CMOS CLOCK DIVIDER

Description

The ICS558-01 accepts a high speed input of either PECL or CMOS, integrates a divider of 1, 2, 3, or 4, and provides four CMOS low skew outputs.

The chip also has output enables so that one, three, or all four outputs can be tri-stated.

Features

  • 16-pin TSSOP package Available in Pb (lead) free package Selectable PECL or CMOS inputs Operates up to 250 MHz Works as a voltage translator Four low skew (.

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Datasheet Details

Part number ICS558-01
Manufacturer ICST
File Size 158.24 KB
Description PECL/CMOS TO CMOS CLOCK DIVIDER
Datasheet download datasheet ICS558-01 Datasheet
Additional preview pages of the ICS558-01 datasheet.

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Full PDF Text Transcription

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www.DataSheet4U.com ICS558-01 PECL/CMOS TO CMOS CLOCK DIVIDER Description The ICS558-01 accepts a high speed input of either PECL or CMOS, integrates a divider of 1, 2, 3, or 4, and provides four CMOS low skew outputs. The chip also has output enables so that one, three, or all four outputs can be tri-stated. The ICS558-01 is a member of the ICS Clock Blocks™ family of clock generation, synchronization, and distribution devices. Features • • • • • • • • • • 16-pin TSSOP package Available in Pb (lead) free package Selectable PECL or CMOS inputs Operates up to 250 MHz Works as a voltage translator Four low skew (<250 ps) outputs Selectable internal divider Operating input voltages of 3.3 V or 5.0 V Operating output voltages of 2.5 V, 3.3 V or 5.
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